Almost all modern bare metal switches are described as PHYless. What does it mean, what we need to consider?
We commonly interconnect network devices for distances below 100 meters with twisted pair or maybe 300 meters over OM3 multimode fiber for 10GBASE-SR. We can extend the span between devices to 10Km for with 10GBASE-LR, 40Km for 10GBase-ER or even 80Km for 10GBase-ZR. However, the signal path doesn’t end at the transceiver. The electronic engineer designing the circuit board must ensure that the signal received by the transceiver is transmitted to the switch ASIC (and vice versa) while maintaining signal integrity and that it a major challenge. Each of the signals traveling along the copper paths has to deal with hazards like electromagnetic interference (EMI), coupling and crosstalk, signal reflections, impedance mismatches, skew, attenuation and a host of other threats as they travel.
An SFP+ transceiver uses an electrical interface called SFI to communicate with the switching ASIC. Modern ASICs (such as Broadcom Trident and Intel Alta family) are capable of receiving and interpreting the SFI-signaled 10Gbps signal directly, such approach is called PHYless. However, if the copper path length is too long to keep signal quality at an acceptable level, we need to place PHY or SERDES, between the transceiver and the ASIC.
These chips can perform some or all of the functions:
Clock recovery and re-timing (common to all chips)
Full electronic dispersion compensation (EDC) – to deal with 10GBASE-LRM
Electrical interface conversion (e.g. SFI to XFI, or SFI to KR)
SERDES – Serial / Parallel conversion (e.g. single lane SFI to four-lane XAUI)
PHY-layer sub-functions like the Physical Coding Sublayer (PCS).
This part is a courtesy of the Network Sherpa blog.
Design Consideration of EDC PHY, Lite PHY, Retimer, and PHYless:
EDC PHY | Lite PHY | Retimer | PHYless |
|
|---|---|---|---|---|
Clock Recovery (Retiming) | X | X | X | |
Equalizer | X | X | X | |
Singal conversion (ex. XLPPI/KR4<->XLAUI, XFI<->SFI) | X | X | ||
Auto Gain Control (Regeneration for amplitude control) | X | |||
Microcontroller and DSP integrated | X | |||
EDC for LRM | X | |||
Roundtrip Latency (40nm, CMOS from BRCM) | 50~70ns | 5ns | <5ns | 0ns |
Power Consumption (40nm, CMOS from BRCM) | 500~700mw/10G port | 300mw/10GE port | <300mw/10GE port | 0mw |
Additional Features |
||||
IEEE 1588 | X | |||
Sync. Ethernet | X | |||
MACSEC | X | |||
FCoE | X | |||
Applications | DSP based EDC PHY. Drive SFP+, QSFP+ Modules and Backplanes. Supports 10GBASE-LRM / MACsec / 1588 / FCoE | Drive SFP+, QSFP+ Modules and Backplanes | Simplex and Duplex Equalizers for Front/Backplane & Chip-2-Chip applications | |
If we compare a PHYless switch with an EDC PHY design, we can summarize PHYless design pros and cons:
Pros:
61W reduction in power consumption (240W->179W).
Lower Latency (50~70ns less).
Increased MTBF and reduced MTTR.
Significant cost reduction.
Cons:
SFP-10G-LRM (Long Reach Multi-mode) transceivers are not supported, use SFP-10G-LR instead.
If you don’t use SFP-10G-LRM transceivers, don’t use Sync Ethernet and MACSEC – you can save a lot with the PHYless switch over EDC PHY box.
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